elec@st

Definitions:

ESD : ElectroStatic Discharge
HBM : (Human Body Model) An electrostatic discharge(ESD) event meeting the waveform criteria specified in standards, approximating the discharge from the fingertip of a typical human being to a grounded device
MM : (Machine Model) An electrostatic discharge (ESD) used to simulate an event occurring from a low resistance source
CDM : (Charge Device Model) An electrostatic discharge (ESD) used to simulate the actual discharge event that occurs when a charged device is quickly discharged to another object at a lower electrostatic potential through a single pin or terminal
EPA : ESD Protected Areas
ESD tester : Equipment that applies a HBM ESD (Thermo Keytek Zapmaster MK.2 SE) or a CDM ESD (Thermo Scientific Orion3) to a component

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Human Body Model (HBM) & Machine Model (MM)
	*SERMA Main Strength on HBM & MM tests* Fast turn around (standard within 1 week) Qualification & Characterization Test standards: MIL, Jedec, ESDA, AEC-Q100 Devices up to 512 channels (upgradeable up to 768) Range HBM 8kV, MM 2kV Static curve trace (5 power supplies) IV curves tracing after each stress Strong IV curves analyser tools
Human Body Model (HBM)	*Systems Strengths ?* IC & discrete devices High IC device pin count test capability Automatic and repeatable tests Weekly waveform verifications Model ? HBM represents the discharge from the fingertip of a standing individual delivered to the device MM represents a discharge from any tool or production equipment to the device	Machine Model (MM)

Charged Device Model (CDM)

	*SERMA Main Strength on CDM tests* Fast turn around (standard within 1 week) Qualification & Characterization Test standards: Jedec, ESDA, AEC-Q100 Range CDM 2kV Test on 0.2mm pitch components Automatic hygrometry control 11GHz scope available (waveform verification at 6GHz) Static curve tracing (with HBM tester)

	Model ? CDM simulates the charging or discharging of an IC through a single pin to a conductive surface, resulting in a fast-rising, high current stress.

Additionnal information

	Specific EPA protected area with compatible ESD floor Generic boards availables (DIL, PGA, QFN ...) for test or curve tracing Mapping of device pins after ESD tests SERMA custom made tools for customers further analysis Work on site possibility (Open Laboratory) Consulting, Training, Audit

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Serma Technologies : BHT - Bâtiment 52 - 7, Parvis Louis Néel – CS20050 - 38040 Grenoble – France

Customer Service: csc@serma.com ; +33 (0)5 57 26 08 88

Definitions:

ESD : ElectroStatic Discharge
LU : (Latch-Up) A state in which a low-impedance path, resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering condition
V_supply overvoltage test: A latch-up test that supplies overvoltage pulses to the Vsupply pin (or pin group) under test
Latch-up tester : Test equipment capable of performing the tests as specified in standards. For devices requiring dynamic testing, required timing signals and logic vectors may be applied by the latch-up tester itself, external equipment, and/or external components as appropriate
Heat source : Equipment capable of heating and maintaining the DUT at the maximum operating temperature specified in the device specification during the latch-up test
EPA : ESD Protected Areas

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Latch-up (LU) Tests
	*SERMA Main Strength* Fast turn around (standard within 1 week) Qualification & Characterization Test standards: Jedec 78, Jedec 78A-E, AEC-Q100 Devices up to 512 channels (upgradeable up to 768) Current injection range: LU 1A Static curve trace and current consumption 5 power supplies + 2 external supplies possibility Temperature tests up to 190°C Application circuit setup.

Test Description Latch-Up is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.

	*Systems Strengths ?* Positive and negative current injections Overvoltage tests on powers Incremental current injections INPUT pins preconditionning High IC device pin count test capability Automatic and repeatable tests	*How ?* Continuity test IDD measurements Current injection (pos/neg) Overvoltage stress Room/High temperature Power supplies Application circuit Basic preconditionning

Additionnal information

	Specific EPA protected area with compatible ESD floor Generic boards availables (DIL, PGA, QFN ...) for test or curve tracing Mapping of device pins after tests Work on site possibility (Open Laboratory) Consulting, Training, Audit

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Serma Technologies : BHT - Bâtiment 52 - 7, Parvis Louis Néel – CS20050 - 38040 Grenoble – France

Customer Service: csc@serma.com ; +33 (0)5 57 26 08 88

Definitions :

FIB : Focused Ion Beam
GDS : (Graphic Database System) Files used in the FIB equipment to navigate to a specific area in the integreted circuit
Circuit Edit : Technique used in new design flow modifications on integreted circuit; This technique can be applied to design optimization changes before final productionin, debugging process or solutions fixes

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	*SERMA Main Strength* Fast turn around (standard within 3 Days) Day night shift Risk assessment Optimization and checking of modification Work on site possibility (Open Laboratory) Data and sample security (pgp, safety box…) Pre and post FIB support (sample prep, electrical characterization).

*Systems Strengths ?* Modification down to 28nm nodes Frontside and backside Edit Package, PCB and wafer up to 8’’ Type of interconnection (Cu, Al) 0,5kV to 30kV beam energy 1pA to 21nA current range IR camera		*Chemistries available ?* Tungsten deposition (2 Ohms/o) Oxide deposition (TEOS, TMCTS) XeF2 (Dielectric & Si trenching) I2 & Cl2 (Aluminum) Water (Copper & Organics) Dx (Copper, Deprocessing) DE (Low-k dielectric)

*How ?* Metal lines cut Metal lines rerouting Selective etching for metal or dielectric Conductive and dielectric deposition Probe pads deposition Cross-sectionning Organics removal		*Main uses ?* Prototyping Mask & IC modification Problem solving Failure analysis Reverse engineering
Circuit-Edit examples

	Using GDS files for navigation

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Customer Service: csc@serma.com ; +33 (0)5 57 26 08 88

SERMA Activities