LU Activities

Definitions:

ESD : ElectroStatic Discharge
LU : (Latch-Up) A state in which a low-impedance path, resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering condition
V_supply overvoltage test: A latch-up test that supplies overvoltage pulses to the Vsupply pin (or pin group) under test
Latch-up tester : Test equipment capable of performing the tests as specified in standards. For devices requiring dynamic testing, required timing signals and logic vectors may be applied by the latch-up tester itself, external equipment, and/or external components as appropriate
Heat source : Equipment capable of heating and maintaining the DUT at the maximum operating temperature specified in the device specification during the latch-up test
EPA : ESD Protected Areas

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Latch-up (LU) Tests
	*SERMA Main Strength* Fast turn around (standard within 1 week) Qualification & Characterization Test standards: Jedec 78, Jedec 78A-E, AEC-Q100 Devices up to 512 channels (upgradeable up to 768) Current injection range: LU 1A Static curve trace and current consumption 5 power supplies + 2 external supplies possibility Temperature tests up to 190°C Application circuit setup.

Test Description Latch-Up is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.

	*Systems Strengths ?* Positive and negative current injections Overvoltage tests on powers Incremental current injections INPUT pins preconditionning High IC device pin count test capability Automatic and repeatable tests	*How ?* Continuity test IDD measurements Current injection (pos/neg) Overvoltage stress Room/High temperature Power supplies Application circuit Basic preconditionning

Additionnal information

	Specific EPA protected area with compatible ESD floor Generic boards availables (DIL, PGA, QFN ...) for test or curve tracing Mapping of device pins after tests Work on site possibility (Open Laboratory) Consulting, Training, Audit

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